There are a number of applications for synchronous operation of digital circuits. Synchronous designs in digital circuits are often implemented with master/slave flip-flops. The master/slave flip-flops are utilized as the synchronizing elements. In one application for synchronous designs in digital circuits, the master/slave flip-flops delay transitions in the state of the circuit until a synchronizing signal, such as a clock signal, arrives. The master/slave flip-flops exhibit a speed overhead that is indicated by the set-up time and the clock-q time (e.g. the propogation delay) of a latching device or register in the master/slave flip-flop. However, the total delay of the register is significantly greater than the sum of the set-up time and the clock-q time of the register.
In order to illustrate the total delay of a register, an example of a 50 megahertz (MHz) system that utilizes a master/slave flip-flop with a specification having a set-up time of 270 picoseconds (ps) and a clock-q time of 430 ps is provided. A total delay time of 700 ps of the 20 nanosecond (ns) cycle time is derived by adding the set-up time and the clock-q time of the register. However, allocating only 270 ps of set-up time for the latching function results in a clock-q time much slower than the 430 ps specification. The optimal speed performance of the register would require in the order of 330 ps for set-up and 570 ps for clock-q. Based on the 330 ps set-up and 570 ps clock-q specifications, 900 ps of the 20 ns cycle time is required.
In addition to providing fast operation for the latching function, it is desirable to integrate additional processing within the flip-flop. For example, implementing a data-path scan multiplexer function within the flip-flop provides utility for testing the circuit. For the system example described above, a total of 19.3 ns remains for execution of a logical operation in the master/slave flip-flop. However, a data-path scan multiplexer may add 250 ps to the set-up time and utilization of a simple multiplexer results in an even greater time requirement. Therefore, it is desirable to integrate functions within a flip-flop without decreasing the speed of the device.